The demand for larger EEPROM memories imposes greater efforts in smaller dimensions for memory cells. If the area of an elementary cell is decreased, and in particular if the dimension of the active area is decreased, there are risks of decreasing the value of the current that flows in the cell during the reading phase. In EEPROM cells the value of the driving current is determined in part by the selection transistor of the bit line that is set in series to the cell itself.
The selection transistor has different design characteristics that are partially contrasting. Particularly, it must have a threshold voltage sufficiently high in order to stop the current when its corresponding cell is not selected, and it must bear a higher current than that of the single cell when it is in a reading phase. In order to be able to bear the driving current of the cell, the active area of the selection transistor has greater dimensions than the dimensions of the active area of the memory cell.
The source of the selection transistor is directly connected to the drain of the floating gate memory cell, preferably it is only one active area. This active area, in the zone of passage from the source area and the drain area, presents two pair of edges, that as a whole, as seen in a top plan view, have a shape substantially similar to that of a funnel just in the zone where the capacitor implants are formed and where the tunnel oxide is grown. This is a very critical zone and during the growth of the oxide crystallographic defects could occur that can create structural stress.